A conventional parallel analog-to-digital converter compares an analog input signal to a series of equally spaced reference voltages. Typically, the reference voltages are produced by a single voltage source and a voltage divider circuit such as a resistive ladder to provide the multiple reference voltage levels. The comparisons are usually provided by a bank of latched comparators. When an analog input signal is present at the input of the comparator bank, all comparators for which the input reference voltage exceeds the analog input voltage produce a low output while the comparators which have a reference voltage input which is below the analog input have a high output. The number of comparators outputting a high voltage level defines the digital output of the device. The outputs of the comparator bank are then encoded to produce a digital output. The encoding logic can produce a standard binary, Gray code or other type of binary coded digital output.
A typical n bit flash converter requires 2.sup.n -1 comparators. Therefore, a flash converter having eight bits of resolution would require 255 comparators, and a comparable amount of associated logic. In comparison to other types of analog-to-digital converters, it can be seen that flash converters require substantially more power, size, wiring and cost. However, on the other hand, since the comparisons are carried out in parallel rather than sequentially, flash converters are substantially faster and can operate at substantially higher frequencies than most other types of analog-to-digital converters.
An improved type of parallel analog-to-digital converter is disclosed in U.S. Pat. No. 4,270,118 issued to Brokaw and entitled PARALLEL ANALOG TO DIGITAL CONVERTER which is owned by the same assignee as the present application. The disclosure of that patent is incorporated herein by reference. That patent discloses a method and mean for reducing the number of comparators necessary in a parallel analog-to-digital converter. The device uses a ladder of differentially coupled transistor pairs. The base of a first transistor of each differential pair is coupled to the input signal (hereinafter called the input transistor). The base of the second of the transistors in each differential pair is coupled to a reference voltage source (hereinafter called the reference transistor). Each differential pair is supplied with a different reference voltage such that the voltage levels are equally spaced by a voltage corresponding to the value of one LSB (least significant bit) apart. The emitters of the two transistors in each differential pair are coupled together and connected to a current sink. The collectors of one of the transistors of the differential pairs are all coupled to a first common point, while the collectors of the other transistors of the differential pairs are all coupled to a second common point. The connections of consecutive differential pairs, however, are alternated such that, if in one differential pair the transistor which has its base coupled to the reference voltage has its collector coupled to the first collector common point, in the adjacent differential pairs, the transistor having its base coupled to the reference voltage has its collector coupled to the second collector common point. This will hereinafter be referred to as interleaving or cross-coupling.
Each differential pair draws a constant current into the current sink, but the amount of current into the current sink drawn through each of the two transistors of the pair depends upon the relative base voltages of the two transistors. As the base voltage of the input transistor of a differential pair (i.e., the input voltage) increases and exceeds the reference voltage supplied at the base of the reference transistor of that differential pair, the input transistor conducts more current through its collector-emitter path than the reference transistor. The opposite holds true for those differential pairs where the input voltage is less than the reference voltage. As each reference threshold of a differential pair is crossed by the input signal, the input transistor will conduct more than the reference transistor, thus increasing the current drawn through the particular collector common point to which its collector is coupled. Thus, since the collectors of the transistors of each differential pair are cross-coupled, as the input crosses the reference voltage threshold of each differential pair (which are set one LSB apart, as noted previously), a greater current is alternately drawn first from one collector common point and then from the other. These collector common points are coupled to the inputs of a comparator. Thus, the output of the comparator switches state every time the input signal crosses a reference threshold.
U.S. Patent Application Ser. No. 07/196,035 of the same inventor as the present application and assigned to the same assignee as the present application, is also incorporated herein by reference.
The parallel analog-to-digital converters of the prior art generally require 2.sup.n-1 comparators to provide n bits of resolution. Additionally, they require at least 2.sup.n-1 resistors and other associated circuitry. The Brokaw invention, U.S. Pat. No. 4,270,118 requires 2.sup.n-1 differential pairs and a substantial number of resistors and other circuit components. In addition to the large size and high cost of producing such parallel analog-to-digital converters, the linearity of such converters is frequently unacceptable due to the difficulty and cost of perfectly matching the large numbers of resistors that are required.
It is an object of the present invention to provide an improved parallel analog to digital converter.
It is another object of the present invention to provide a parallel analog-to-digital converter which utilizes fewer comparators for a given resolution than is known in the prior art.
It is yet another object of the present invention to provide a parallel analog-to-digital converter utilizing differential pairs which requires fewer differential pairs than is known in the prior art.
It is a further object of the present invention to provide a parallel analog to-digital converter comprising a matrix of differential pairs.
It is one more object of the present invention to provide a parallel analog-to-digital converter providing additional resolution without the need for additional differential pairs.
It is yet another object of the present invention to provide a parallel analog to-digital converter which utilizes fewer reference voltage levels and therefore fewer resistors than prior art devices.
It is a further object of the present invention to provide a parallel analog-to-digital converter having improved linearity.
It is another object of the present invention to provide a parallel analog-to-digital converter in which it is practical to laser-trim the resistors to provide increased linearity since there are fewer resistors than in the prior art.